High resolution, high speed analog-to-digital converters (ADCs) can require buffers to isolate a high impedance track-and-hold (TAH) stage from one or more sample-and-hold (SAH) stages preceding the ADC. In some cases, buffers can be used to isolate successive SAH stages. Such buffer implementations can be a key component in enabling and advancing high speed communication (e.g., 100 Gigabit Ethernet) networks and systems. For example, a 28 Gbps serial link communication receiver might require multiple successive approximation register (SAR) ADCs, each with one or more buffers exhibiting at least the following characteristics: wide bandwidth, very fast large signal settling and slewing (e.g., low output impedance), high linearity over the full analog input signal, low noise, high power supply rejection, and high input impedance over the wide bandwidth (e.g., near or in excess of the Nyquist rate). Such receivers might also demand the buffer exhibit low power consumption (e.g., 1V supply voltage), which further requires the buffer gain to be near unity.
A buffer exhibiting the aforementioned characteristics is often referred to herein as a buffer having a “gain boost configuration”. Further details regarding general approaches to making and using a buffers with gain boost configuration are described in U.S. application Ser. No. 14/614,257, now U.S. Pat. No. 9,432,000, entitled “LOW POWER BUFFER WITH GAIN BOOST”. The disclosed gain boost configuration has a first transistor that receives an input signal and a second transistor that receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal and to generate a negative drain transconductance (e.g., gds) effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In one or more embodiments, the gain boost configuration can be deployed in a full differential implementation. In one or more embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities. The intrinsic gain of the gain boost configuration can be set near a target gain (e.g., unity) by simulating the buffer over worst case process, voltage, temperature, and device mismatch (e.g., PVTM) variations and adjusting various design attributes (e.g., transistor sizes) to meet or exceed the target gain at all corners. However, the resulting actual gain of the manufactured buffer at a given operating condition can vary significantly from the target gain. As the speed of the underlying circuit fabrication processes increases (e.g., with the advancement of low power, high speed communication system implementations), such gain variations also increase.
Techniques are needed address the problem of implementing a low power buffer that can operate at a target gain under various process, voltage, temperature, and device mismatch conditions. None of the aforementioned legacy approaches achieve the capabilities of the herein-disclosed techniques for low power buffers with dynamic gain control. Therefore, there is a need for improvements.